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ÇѱÛÁ¦¸ñ(Korean Title) |
Àü¿ªÀûÀÎ ¹è¸®¾î µ¿±âȸ¦ ¼öÇàÇÏÁö ¾Ê´Â È¿À²ÀûÀÎ BSP ¿¬»ê ±â¾÷ |
¿µ¹®Á¦¸ñ(English Title) |
An Efficient BSP Computation without Global Barrier Synchronization |
ÀúÀÚ(Author) |
±èÁø¼ö
ÇϼøÈñ
ÀüÁÖ½Ä
Jinsoo Kim
Soonhoi Ha
Chu Shik Jhon
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¿ø¹®¼ö·Ïó(Citation) |
VOL 25 NO. 07 PP. 0655 ~ 0667 (1998. 07) |
Çѱ۳»¿ë (Korean Abstract) |
BSP (Bulk Synchronous Parallel) ¿¬»ê ¸ðµ¨Àº ´Ù¾çÇÑ º´·Äó¸® ±¸Á¶»ó¿¡¼ È¿À²ÀûÀÌ°í À̽ļº ³ôÀº º´·Ä ÇÁ·Î±×·¥À» °³¹ßÇϴµ¥ ¸Å¿ì À¯¿ëÇÏ´Ù. ±×·¯³ª BSP ¸ðµ¨¿¡¼ »ç¿ëµÇ´Â ¹è¸®¾î µ¿±âÈ´Â ¸Þ½ÃÁö ÆÐ½Ì ±¸Á¶ÀÇ °æ¿ì »ó´ëÀûÀ¸·Î Å« ¿À¹öÇìµå¸¦ ¼ö¹ÝÇÑ´Ù. ÀÌ¿¡ µû¶ó º» ³í¹®¿¡¼´Â ¸Þ½ÃÁö ÆÐ½Ì ±¸Á¶»ó¿¡¼ BSP ¿¬»ê ¸ðµ¨ÀÇ È¿À²ÀûÀÎ ±¸ÇöÀ» À§ÇØ BSP ¸ðµ¨ÀÇ ¹è¸®¾î µ¿±âÈ Á¶°ÇÀ» ¿ÏȽÃŲ ¿¬¼º ¹è¸®¾î µ¿±âÈ ±â¹ýÀ» Á¦¾ÈÇÑ´Ù. Á¦¾ÈÇÏ´Â ±â¹ýÀº ±âÁ¸ÀÇ ¹æ¹ý°ú´Â ´Þ¸® Àü¿ªÀûÀÎ ¹è¸®¾î µ¿±âȸ¦ ¼öÇàÇÏÁö ¾Ê°í, °¢°¢ÀÇ ÇÁ·Î¼¼¼µéÀÌ ¿ÜºÎ µ¥ÀÌŸ¸¦ ÂüÁ¶ÇÒ °æ¿ì¿¡¸¸ ¼Û½Å ÇÁ·Î¼¼¼¿Í µ¿±âÈ°¡ ÇàÇØÁöµµ·Ï ÇÑ´Ù. µû¶ó¼ °¢ ÇÁ·Î¼¼¼µéÀº ÀÚ½ÅÀÇ »ó´ëÀûÀÎ ¼öÇà ¼Óµµ¿Í µ¿±âÈ ¿ä°Ç¿¡ µû¶ó ¼·Î ´Ù¸¥ ¼öÆÛ½ºÅÜÀ» ¼öÇàÇÏ°Ô µÇ¸ç, ¿¬¼º ¹è¸®¾î µ¿±âÈ ±â¹ýÀÌ À̵鰣 µ¥ÀÌŸ Á¢±ÙÀÇ ÀÏ°ü¼ºÀ» º¸ÀåÇÑ´Ù. IBM SP2 »ó¿¡¼ÀÇ ½ÇÇè °á°ú 32°³ÀÇ ÇÁ·Î¼¼¼µé »ç¿ëÇÑ °æ¿ì ±âÁ¸ÀÇ ±¸Çö ¹æ¹ý¿¡ ºñÇØ FT¿¡¼´Â 45.2%¿¡¼ 61.5%, LU¿¡¼´Â 28.6%¿¡ 49.0%ÀÇ µµÀÍÈ ½Ã°£ÀÌ °¨¼ÒµÊÀ» È®ÀÎÇÏ¿´´Ù. |
¿µ¹®³»¿ë (English Abstract) |
The Bulk Synchronous Parallel (BSP) model of computation can be used to develop efficient and portable programs for a range of machines and applications. However, the cost of the barrier synchronization used in the BSP model is relatively expensive for message-passing architectures. In this paper, we relax the barrier synchronization constraint in the BSP model for the efficient implementation on message-passing architectures.
In our relaxed barrier synchronization, the synchronization occurs at the time of accessing non-local data only between the producer and the consumer processors, eliminating the exchange of global information. Because processors are not globally synchronized, each processor may execute different superstep according to its relative speed and the synchronization requirements.
From the experimental evaluations on IBS SP2, we have observed that the relaxed barrier synchronization reduces the average synchronization time by 45.2% to 61.5% in FT, and 28.6% to 49.0% in LU with 32 processors. |
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